A masked read-only memory (hereinafter referred to as a mask ROM) is an information storage device into which information is written through the use of a particular photomask during fabrication of the memory device. Once information is thus written into the mask ROM, the information is retained throughout use of the memory device. Such a memory device is useful especially for fixedly storing any program typically in a microcomputer system.
Among various types of semiconductor memory devices using mask ROMs which are presently in use is a device which has incorporated therein a redundant error detect/correct circuit operative to detect bits in error in the mask ROM used as an information memory array and to correct the detected errors. Such a memory device is advantageous principally for the purpose of increasing the yield of production of memory devices. The error detect/correct circuit of this memory device includes a parity memory array comprised of parity check bits typically arranged on the basis of a Hamming error detect/correct code used as the error detection and correction algorithm.
Provision of the parity bits additionally in a memory device however gives rise to an increase in the area which the memory device occupies on a semiconductor chip. The overhead thus required for the implementation of an error detect/correct circuit increases at a rate which depends on the ratio between the number of the information bits forming a single data word and the number of the parity bits to be added to the information bits. If the information bits to be read out during each read cycle is assumed to include a single bit in error, the following relationship occurs between the number of the information bits and the number of the parity bits to be added to the information bits.
______________________________________ Number of Information Bits Number of Parity Bits ______________________________________ 8 5 16 6 24 6 32 7 40 7 48 8 56 8 64 8 ______________________________________
An increase in the number of the information bits to be read out during each read cycle represents an increase in the number of the information detect means, viz., the sense amplifiers to be provided in association with the information. This in turn results in an increase in the proportion of the area occupied by the sense amplifiers in the total area of the semiconductor chip and further in an increase in the amount of power dissipation by the chip. To provide a tradeoff under such circumstances, thirty two or less bits are commonly used as the information bits to be form a single data word to read out during each read cycle. Where thirty two bits are thus used as the information bits to form a single data word, the area of the chip required for the memory device using parity bits becomes (32+7)/32=1.22 times the area required for the information bits. This means an overhead of about 22 per cent for the area required for the memory array for the parity bits alone. Taking into consideration the areas which are further required for the provision of the circuits for the detection and correction of errors and the sense amplifiers associated with the memory array for the parity bits, the final overhead of the chip will total up to about 25 per cent or even more. A further drawback is in that the detection and correction of errors is performed by a number of logic gates which results in an increase in the access time.
It is, accordingly, an important object of the present invention to provide an improved semiconductor memory device using a mask ROM as an information memory array and featuring an error detect/correct circuit which requires only a minimum overhead on a semiconductor chip and which permits of significant improvement in the yield of the memory device.
Another important object of the present invention is to provide an improved semiconductor memory device with integrated error detection and correction functions, the memory device having an error detect/correct circuit which is capable of detecting and correcting errors in the information bits without the penalty of increasing the access time.